1. Field of the Invention
The present invention generally relates to the field of integrated circuit physical design. In particular, the present invention is directed to a method for designing an integrated circuit with inserted loops and a computer readable medium containing computer executable instructions as well as a system for designing an integrated circuit with inserted loops.
2. Description of Background
As the physical dimensions of VLSI (Very Large Scale Integrated Circuits) continue to shrink, it has become increasingly difficult to manufacture such integrated circuits in a reliable fashion. The sensitivity of a VLSI design to random defects increases as feature widths and spacing between features grow smaller. In addition, the presence of single vias, i.e. of inter-layer connectors through a single via, is particularly undesirable. From the perspective of random-defect yield, a single via is especially likely to cause a chip failure because a spot-defect landing on a single via will create an open circuit. From the perspective of systematic yield, if vias are difficult to manufacture in a given process, a poorly created single via can cause a circuit open or a highly resistive connection, which can cause a circuit to fail. New manufacturing processes are particularly sensitive to yield problems that are related to the formation of vias.
US 2006/0265684 A1 discloses an automated method for reducing integrated circuit design sensitivity to manufacturing defects and increasing integrated circuit reliability by using existing router technology to increase redundancy of inter-layer connectors, i.e. vias, and intra-layer connectors, e.g. wire segments, in order to enhance circuit reliability and yield. Once the initial routing is completed, single vias, i.e. single vias used to make an inter-layer connection, are identified. Then, a specific single via is selected and temporarily blocked. Specifically, the selected single via is marked within the routing program as not available for connecting a first element to a second element, the first and second elements being a wire, pin, device etc. The single via is also preferably coded as “must keep” so that the routing program will not remove the original single via in order to form another path. Then, the existing routing program identifies an available alternate route for a connection between the first and second elements and inserts a second path therein. The second path comprises a loop that extends from the first element to the second element and comprises at least one additional via and an additional intra-layer connector, e.g. a wire segment. Once the second path is inserted, the single via is unblocked. Thus, the first element and the second element are connected by both first and second paths, i.e. redundant paths. The process is repeated for each single via identified. These redundant paths are used to reduce the integrated circuit's sensitivity to manufacturing defects that may be caused by a potential block in the single via.
When implementing a method for reducing integrated circuit design sensitivity by using existing router technology to increase redundancy of inter-layer connectors, i.e. vias, and intra-layer connectors, e.g. wire segments; one is faced with several kinds of problems: DRC violations, e.g. a minimum of enclosed area violations, might be introduced by the router technology. Timing violations might be introduced as well because the resistance and the capacitance of the integrated circuit's nets are changed when loops are inserted. Especially the capacitance increase is not limited to nets where loops are inserted, but also comprises nets adjacent to the newly inserted segments forming the loop. ECO (Engineering Change Order) routing becomes much harder because the inserted loops consume routing space.
For these reasons, a need exists for improved structures for implementing redundant vias in an integrated circuit physical design process, in order to reduce the complexity of the manufacturing process, maintain high wiring density, and maximize manufacturing yield.